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The End of EDA: Why AI Will Eat the $100B Chip Design Stack
For decades, hardware engineering has been mediated by tools. EDA stacks, PDKs, simulation environments — these defined not just workflows, but
Read post →Selected writing on DFM, UCIe, advanced packaging, yield learning, and architecture decisions that affect real chiplet schedules.
For decades, hardware engineering has been mediated by tools. EDA stacks, PDKs, simulation environments — these defined not just workflows, but
Read post →The Industry Assumption
Read post →Chiplet Summit 2026 · Technical Talk
Read post →In this podcast episode, we explore the fascinating journey of "chipletization" from its academic roots at Stanford University to becoming the...
Read post →How modular silicon became inevitable in the age of AI
Read post →At the recent Open Compute Project (OCP) Global Summit, the
Read post →As 2.5D systems bring GPUs, CPUs, HBM, and other chiplets closer together, thermal management stops being just a heatsink problem and becomes a...
Read post →🔥 The Industry Has Crossed a Line
Read post →This question comes quite often. When is a chip a chiplet? The team at the Chiplet Design Exchange (CDX) under the Open Compute Project (OC)...
Read post →The industry shift from monolithic chips to disaggregated chiplets, bound together through Heterogeneous Integration (HI), marks a significant...
Read post →IEEE2416 'Standard for Power Modeling to Enable System-Level Analysis' became official in May 2019. Among its many cool aspects it defines a new way...
Read post →The CDX (Chiplet Design eXchange) workstream under Open Compute Project’s ODSA sub-project is actively looking at the problems of chiplet...
Read post →If your team is evaluating chiplet partitioning, UCIe, test vehicles, or packaging tradeoffs, we can move from writing to working session quickly.