The industry shift from monolithic chips to disaggregated chiplets, bound together through Heterogeneous Integration (HI), marks a significant advance in semiconductor design. This approach allows for increased discrete functionality and the use of different technology nodes within a single package. However, the resulting chiplet-based systems are larger and significantly more complex, driving power and thermal modeling and analysis complexity to an exponential level. Given the infeasibility of designing for the absolute "worst case" in these intricate systems, the industry must move toward Scenario Power and Thermal Analyses.

The Shift to Chiplets and Heterogeneous Integration (HI)

Die disaggregation breaks down a monolithic chip into smaller components, each potentially created at a different technology node. Heterogeneous Integration then brings these chiplets together into a single package, along with components that have varying usage profiles, reliability limits, and distinct power requirements.

This co-integration creates three core new challenges:

• The system complexity makes traditional power and thermal analysis impractical.

• The diverse component properties (e.g., varying reliability limits) require a new approach to modeling.

• Standard worst-case power and thermal analyses must be replaced by a more nuanced, scenario-based exploration.

The Evolving Thermal Design Flow

The standard ASIC design flow, which concludes with sign-off after implementation, is insufficient for chiplets. The Typical HI Chiplet Flow introduces thermal considerations earlier in the process:

• ASIC Flow: RTL design, Implementation, Sign off.

• HI Chiplet Flow: RTL design, Implementation, Architecture, Floorplanning, Power analysis, Package design, Thermal analysis, Sign off.

This new process emphasizes early planning for Sign off!. The methodology involves a progressive analysis to ensure thermal limits are met.

Key Thermal Challenges in HI Systems

The complex nature of HI introduces specific thermal challenges that must be addressed through detailed modeling.Transient Thermal Behavior

Steady-state analysis serves as an early indicator for potential thermal issues but is not sufficient for a complete solution. Transient analysis is required to determine the true, time-dependent thermal behavior of the system, capturing how heat evolves and dissipates under various load conditions.

Dense Heterogeneous Integration brings chiplets into close proximity, resulting in significant thermal coupling. Understanding the temporal heat diffusion between these components is critical for effective power and thermal management.

The thermal landscape is complex, as new paths for heat flow emerge:

• Lateral heat flow becomes a major factor in heat dissipation.

• Thermal coupling occurs through both the interposer and the heatsink.

Detailed and progressively refined thermal models are necessary to accurately capture this complex heat transfer.

Power Management Strategies for Heat Reduction

Controlling heat is intrinsically linked to managing power. For chiplets, power distribution and control systems must adapt.

The choice of Voltage Regulator Modules (VRMs) directly impacts a system’s cost, design complexity, and power control effectiveness:

• Common VRM: Using a single VRM for multiple chiplets is simpler and lower cost, leading to easier package design. However, it results in a "lowest denominator VRM control" and worse power management.

• Separate VRMs: Assigning a dedicated VRM to each chiplet allows for optimized control and better power management. This comes with the trade-offs of higher cost and more difficult package design.

Scenario-Based Analysis: The Path to Optimal Design

A chiplet system will operate under at least two completely different Power and Thermal Scenarios (e.g., maximum load vs. idle or specific mixed-load conditions). Since designing for the absolute theoretical worst case is not feasible, full system scenario exploration is required for an optimal product.

This requires a comprehensive analysis flow that ties together different design aspects:

1. Chiplet Floorplan Scenarios (e.g., Scenario 1).

2. System 3D Model (e.g., Scenario 2).

3. Chiplet Power Analysis (e.g., Scenario 3).

4. System Power Supply Definition (e.g., Scenario 4).

5. Chiplet Power Density Scenarios (e.g., Scenario 5).

6. System Scenario Thermal Analysis.

Avoid Costly Thermal Issues

To successfully bring an HI chiplet system to market, designers must avoid costly thermal issues by integrating a rigorous thermal methodology into the design process. This means:

• Starting early with detailed models, a defined set of scenarios, and a clear understanding of thermal limits.

• Progressively refining these models and scenarios throughout implementation.

• Verifying the system’s performance at the final Sign-off.

The mandate for the chiplet era is clear: Plan early for sign off!.