At the recent Open Compute Project (OCP) Global Summit, the Chiplet Design Exchange (CDX) work stream unveiled significant strides in advancing chiplet design standardization and practical implementation. David Ratchkov, CDX co-lead, and Seungmin Woo, a PhD student from the Georgia Institute of Technology, showcased how the CDX consortium is bridging the gap between theoretical specifications and physical system realization.

Pushing Standards Forward

CDX is actively expanding the CDXML specification to create a comprehensive digital twin framework for chiplet-based systems. According to Ratchkov, this effort focuses on filling gaps in existing standards to ensure interoperability. Key updates highlighted include:

• Material Design Kits (MDK): Now available for simulating material properties

• Assembly Design Kits (ADK): Released to model complex 3D packaging assembly

• Test Design Kits (TDK 2.0): Under development to automate test insertion workflows, reducing manual efforts in data sheet analysis

• SIP Kit: Currently defining electrical interfaces, with future versions aiming to address protocol compatibility

System Realization on Glass

To validate these standards, CDX presented a demonstration design featuring a high-performance architecture integrated on a glass interposer. Woo detailed the design process, which utilizes open-source tools such as OpenROAD and OpenRAM. The demo configuration includes:

• Four CPU chiplets

• Four HBM4 memory stacks

• Four IO chiplets

Technical Challenges and Future Optimization

The presentation emphasizes that the CDX demonstration design currently consumes approximately 600 watts of power. The architecture relies on on-package Integrated Voltage Regulators (IVRs) to convert power efficiently for components like the core, HBM, and UCIe interfaces. However, preliminary simulations indicate a critical thermal issue, with temperatures reaching 145°C. As a result, the team is actively working on power reduction strategies and developing improved cooling solutions to bring the system within safe operating parameters.

Call to Action for Industry Collaboration

CDX is actively seeking partnership and validation from the broader industry to refine these standards. They invite companies with UCIe or HBM files to simulate their own designs using CDX models to check for compatibility and signal integrity . Furthermore, CDX encourages engineers and researchers interested in standardizing chiplet workflows and contributing to the demo design to join their weekly work stream meetings, held on Thursdays at 10:00 a.m. Pacific.