What is a Chiplet

This question comes quite often. When is a chip a chiplet? The team at the Chiplet Design Exchange (CDX) under the Open Compute Project (OC) struggled with this question as well.

The team wanted to define a workflow for integrating chiplets. This eventually led to the “GUIDE TO INTEGRATION WORKFLOWS FOR HETEROGENEOUS CHIPLET SYSTEMS” white paper contributed to OCP in 2024 [paper]. But first, we needed to answer that question.

Integrating multiple chips in a package has been done for a long time. This is known as System-in-Package, or SiP for short. SiPs will integrate chips from multiple vendors. Typically, the integrator will obtain unpackaged dies, known as bare dies, and integrate them into the same package. So instead of having multiple packaged chips on a board, these dies now live in a single package, reducing the board's overall footprint.

Chiplets take this one step further. Dies that are meant to live in a package are designed to communicate with components outside of their package - all communication links can drive signals over long distances. But when dies are inside the same package, the links will be deterministically shorter, so the design requirements for these links can be relaxed.

This design style led to the narrowing of the definition of what constitutes a chiplet. In short, a chiplet is a die with communication links that can communicate only within the same package.

HBM - The OG Chiplet

The first chiplet, and one of the most widely used, was High Bandwidth Memory (HBM).

Bump map of HBM3. Signals are shown in white, Power and Ground are in red and green.

HBM is meant to live on an interposer with other dies. With the exception of the few test signals, the main signals, such as strobe, data, address, ECC, etc. reach a length of about 6mm to 7mm. But most importantly, do not have the strength to communicate outside of the package.

HBM itself combined multiple dies, stacked vertically on a base die. Each of these is a chiplet in its own righ .

Chiplet Interfaces

As we discussed earlier, the communication interfaces of a chiplet are purposely designed to communicate over short distances. But what are they?

There are two major types - parallel and serial. A parallel interface sends its bits across multiple wires, while a serial interface sends all its bits across two wires.

The original parallel chiplet interface was Bunch-of-Wires, developed at OCP. It is a simple Double Data Rate (DDR) interface. Later came the Universal Chiplet Interface (UCIe), which defined different bus-width versions, package options, and bump maps. Today, it also includes a 3D version for use with dies stacked vertically.

Serial interfaces continue to be SERDE- based, but with greatly simplified circuit designs optimized for the much shorter reach required by a chiplet.

In summary, a chiplet is defined as a die whose communication links are designed to communicate only within the same package, unlike traditional System-in-Package (SiP) chips that have links built for long distances outside the package. This shorter, deterministic distance allows for relaxed design requirements for the links. Chiplets use short-distance interfaces which are categorized as parallel, such as the original Bunch-of-Wires and the more recent Universal Chiplet Interface (UCIe), or serial interfaces that are simplified SERDES-based designs.